A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS

Shih Hao Huang; Zheng Hao Hung; Wei Zen Chen

doi:10.1109/ASSCC.2014.7008869

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS

Shih Hao Huang, Zheng Hao Hung, Wei Zen Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μA_pp at bit-error-rate of less than 10^-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm².

Original language	English
Title of host publication	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	97-100
Number of pages	4
ISBN (Electronic)	9781479940905
DOIs	https://doi.org/10.1109/ASSCC.2014.7008869
State	Published - 13 Jan 2015
Event	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan Duration: 10 Nov 2014 → 12 Nov 2014

Publication series

Name	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/Territory	Taiwan
City	Kaohsiung
Period	10/11/14 → 12/11/14

Keywords

Monolithic optical receiver
comparator
high-density optical interconnect
photodetector (PD)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ASSCC.2014.7008869

Cite this

Huang, S. H., Hung, Z. H., & Chen, W. Z. (2015). A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers (pp. 97-100). Article 7008869 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2014.7008869

Huang, Shih Hao ; Hung, Zheng Hao ; Chen, Wei Zen. / A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 97-100 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

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abstract = "This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.",

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Huang, SH, Hung, ZH & Chen, WZ 2015, A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. in 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers., 7008869, 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 97-100, 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, Kaohsiung, Taiwan, 10/11/14. https://doi.org/10.1109/ASSCC.2014.7008869

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. / Huang, Shih Hao; Hung, Zheng Hao; Chen, Wei Zen.
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 97-100 7008869 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.

AB - This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.

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KW - high-density optical interconnect

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Huang SH, Hung ZH, Chen WZ. A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 97-100. 7008869. (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). doi: 10.1109/ASSCC.2014.7008869

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS

Abstract

Publication series

Conference

Keywords

UN SDGs

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