A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS

Shih Hao Huang, Zheng Hao Hung, Wei Zen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.

Original languageEnglish
Title of host publication2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages97-100
Number of pages4
ISBN (Electronic)9781479940905
DOIs
StatePublished - 13 Jan 2015
Event2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan
Duration: 10 Nov 201412 Nov 2014

Publication series

Name2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/TerritoryTaiwan
CityKaohsiung
Period10/11/1412/11/14

Keywords

  • comparator
  • high-density optical interconnect
  • Monolithic optical receiver
  • photodetector (PD)

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