A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

Fang Ju Ku; Tung Yu Wu; Yen Chin Liao; Hsie-Chia Chang; Wing Hung Wong; Chen-Yi Lee

doi:10.1109/VLSI-DAT.2018.8373265

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

Fang Ju Ku, Tung Yu Wu, Yen Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.

Original language	English
Title of host publication	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538642603
DOIs	https://doi.org/10.1109/VLSI-DAT.2018.8373265
State	Published - 5 Jun 2018
Event	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan Duration: 16 Apr 2018 → 19 Apr 2018

Publication series

Name	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Conference

Conference	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Country/Territory	Taiwan
City	Hsinchu
Period	16/04/18 → 19/04/18

Keywords

Bayesian sequential partition
big data analysis
bit-plane
hardware architecture

Access to Document

10.1109/VLSI-DAT.2018.8373265

Cite this

Ku, F. J., Wu, T. Y., Liao, Y. C., Chang, H.-C., Wong, W. H., & Lee, C.-Y. (2018). A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373265

@inproceedings{710f9315e93249a1b12a14a287f4391d,

title = "A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS",

abstract = "This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.",

keywords = "Bayesian sequential partition, big data analysis, bit-plane, hardware architecture",

author = "Ku, {Fang Ju} and Wu, {Tung Yu} and Liao, {Yen Chin} and Hsie-Chia Chang and Wong, {Wing Hung} and Chen-Yi Lee",

year = "2018",

month = jun,

day = "5",

doi = "10.1109/VLSI-DAT.2018.8373265",

language = "English",

series = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

address = "美國",

note = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",

}

Ku, FJ, Wu, TY, Liao, YC, Chang, H-C, Wong, WH & Lee, C-Y 2018, A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. in 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, 16/04/18. https://doi.org/10.1109/VLSI-DAT.2018.8373265

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. / Ku, Fang Ju; Wu, Tung Yu; Liao, Yen Chin et al.
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

AU - Ku, Fang Ju

AU - Wu, Tung Yu

AU - Liao, Yen Chin

AU - Chang, Hsie-Chia

AU - Wong, Wing Hung

AU - Lee, Chen-Yi

PY - 2018/6/5

Y1 - 2018/6/5

N2 - This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.

AB - This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.

KW - Bayesian sequential partition

KW - big data analysis

KW - bit-plane

KW - hardware architecture

UR - http://www.scopus.com/inward/record.url?scp=85049300057&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2018.8373265

DO - 10.1109/VLSI-DAT.2018.8373265

M3 - Conference contribution

AN - SCOPUS:85049300057

T3 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

SP - 1

EP - 4

BT - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Y2 - 16 April 2018 through 19 April 2018

ER -

Ku FJ, Wu TY, Liao YC, Chang HC, Wong WH, Lee CY. A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). doi: 10.1109/VLSI-DAT.2018.8373265

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this