@inproceedings{710f9315e93249a1b12a14a287f4391d,
title = "A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS",
abstract = "This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.",
keywords = "Bayesian sequential partition, big data analysis, bit-plane, hardware architecture",
author = "Ku, {Fang Ju} and Wu, {Tung Yu} and Liao, {Yen Chin} and Hsie-Chia Chang and Wong, {Wing Hung} and Chen-Yi Lee",
year = "2018",
month = jun,
day = "5",
doi = "10.1109/VLSI-DAT.2018.8373265",
language = "English",
series = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--4",
booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",
address = "美國",
note = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",
}