A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC

Jen Hung Chi*, Shih Hsuan Chu, Tsung Heng Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations

Abstract

A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm 2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.

Original languageEnglish
Title of host publicationESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages222-225
Number of pages4
DOIs
StatePublished - 2010
Event36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
Duration: 14 Sep 201016 Sep 2010

Publication series

NameESSCIRC 2010 - 36th European Solid State Circuits Conference

Conference

Conference36th European Solid State Circuits Conference, ESSCIRC 2010
Country/TerritorySpain
CitySevilla
Period14/09/1016/09/10

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