A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC

Jen Hung Chi; Shih Hsuan Chu; Tsung Heng Tsai

doi:10.1109/ESSCIRC.2010.5619889

A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC

Jen Hung Chi^*, Shih Hsuan Chu, Tsung Heng Tsai

^*Corresponding author for this work

Institute of Pioneer Semiconductor Innovation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm ². After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.

Original language	English
Title of host publication	ESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages	222-225
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2010.5619889
State	Published - 2010
Event	36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain Duration: 14 Sep 2010 → 16 Sep 2010

Publication series

Name	ESSCIRC 2010 - 36th European Solid State Circuits Conference

Conference

Conference	36th European Solid State Circuits Conference, ESSCIRC 2010
Country/Territory	Spain
City	Sevilla
Period	14/09/10 → 16/09/10

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10.1109/ESSCIRC.2010.5619889

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title = "A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC",

abstract = "A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm 2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.",

author = "Chi, {Jen Hung} and Chu, {Shih Hsuan} and Tsai, {Tsung Heng}",

year = "2010",

doi = "10.1109/ESSCIRC.2010.5619889",

language = "English",

isbn = "9781424466641",

series = "ESSCIRC 2010 - 36th European Solid State Circuits Conference",

pages = "222--225",

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note = "null ; Conference date: 14-09-2010 Through 16-09-2010",

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AU - Chi, Jen Hung

AU - Chu, Shih Hsuan

AU - Tsai, Tsung Heng

PY - 2010

Y1 - 2010

N2 - A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm 2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.

AB - A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm 2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.

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U2 - 10.1109/ESSCIRC.2010.5619889

DO - 10.1109/ESSCIRC.2010.5619889

M3 - Conference contribution

AN - SCOPUS:78650352692

SN - 9781424466641

T3 - ESSCIRC 2010 - 36th European Solid State Circuits Conference

SP - 222

EP - 225

BT - ESSCIRC 2010 - 36th European Solid State Circuits Conference

Y2 - 14 September 2010 through 16 September 2010

ER -

A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC

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