TY - GEN
T1 - A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC
AU - Chi, Jen Hung
AU - Chu, Shih Hsuan
AU - Tsai, Tsung Heng
PY - 2010
Y1 - 2010
N2 - A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm 2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.
AB - A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm 2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.
UR - http://www.scopus.com/inward/record.url?scp=78650352692&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2010.5619889
DO - 10.1109/ESSCIRC.2010.5619889
M3 - Conference contribution
AN - SCOPUS:78650352692
SN - 9781424466641
T3 - ESSCIRC 2010 - 36th European Solid State Circuits Conference
SP - 222
EP - 225
BT - ESSCIRC 2010 - 36th European Solid State Circuits Conference
T2 - 36th European Solid State Circuits Conference, ESSCIRC 2010
Y2 - 14 September 2010 through 16 September 2010
ER -