A 160-GHz frequency-translation phase-locked loop with RSSI assisted frequency acquisition

Wei-Zen Chen; Tai You Lu; Yan Ting Wang; Jhong Ting Jian; Yi Hung Yang; Kai Ting Chang

doi:10.1109/TCSI.2013.2295016

A 160-GHz frequency-translation phase-locked loop with RSSI assisted frequency acquisition

Wei-Zen Chen, Tai You Lu, Yan Ting Wang, Jhong Ting Jian, Yi Hung Yang, Kai Ting Chang

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm². The PLL locking time is less than 3 μ s. This chip drains 24 mW from a 1.2 V power supply.

Original language	English
Article number	6728756
Pages (from-to)	1648-1655
Number of pages	8
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	61
Issue number	6
DOIs	https://doi.org/10.1109/TCSI.2013.2295016
State	Published - Jun 2014

Keywords

Harmonic mixer
PLL
RSSI
tripler

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10.1109/TCSI.2013.2295016

Cite this

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title = "A 160-GHz frequency-translation phase-locked loop with RSSI assisted frequency acquisition",

abstract = "A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm2. The PLL locking time is less than 3 μ s. This chip drains 24 mW from a 1.2 V power supply.",

keywords = "Harmonic mixer, PLL, RSSI, tripler",

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AU - Chen, Wei-Zen

AU - Lu, Tai You

AU - Wang, Yan Ting

AU - Jian, Jhong Ting

AU - Yang, Yi Hung

AU - Chang, Kai Ting

PY - 2014/6

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AB - A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm2. The PLL locking time is less than 3 μ s. This chip drains 24 mW from a 1.2 V power supply.

KW - Harmonic mixer

KW - PLL

KW - RSSI

KW - tripler

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JF - IEEE Transactions on Circuits and Systems I: Regular Papers

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A 160-GHz frequency-translation phase-locked loop with RSSI assisted frequency acquisition

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Keywords

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