A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications

Xin Ru Lee; Chih Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ESSCIRC.2015.7313837

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications

Xin Ru Lee^*, Chih Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.

Original language	English
Title of host publication	ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
Editors	Franz Dielacher, Wolfgang Pribyl, Gernot Hueber
Publisher	IEEE Computer Society
Pages	96-99
Number of pages	4
ISBN (Electronic)	9781467374705
DOIs	https://doi.org/10.1109/ESSCIRC.2015.7313837
State	Published - 14 Sep 2015
Event	41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria Duration: 14 Sep 2015 → 18 Sep 2015

Publication series

Name	European Solid-State Circuits Conference
Volume	2015-October
ISSN (Print)	1930-8833

Conference

Conference	41st European Solid-State Circuits Conference, ESSCIRC 2015
Country/Territory	Austria
City	Graz
Period	14/09/15 → 18/09/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ESSCIRC.2015.7313837

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Lee, X. R., Yang, C. W., Chen, C.-L., Chang, H.-C., & Lee, C.-Y. (2015). A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. In F. Dielacher, W. Pribyl, & G. Hueber (Eds.), ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference (pp. 96-99). Article 7313837 (European Solid-State Circuits Conference; Vol. 2015-October). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2015.7313837

Lee, Xin Ru ; Yang, Chih Wen ; Chen, Chih-Lung et al. / A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. editor / Franz Dielacher ; Wolfgang Pribyl ; Gernot Hueber. IEEE Computer Society, 2015. pp. 96-99 (European Solid-State Circuits Conference).

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title = "A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications",

abstract = "In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.",

author = "Lee, {Xin Ru} and Yang, {Chih Wen} and Chih-Lung Chen and Hsie-Chia Chang and Chen-Yi Lee",

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Lee, XR, Yang, CW, Chen, C-L, Chang, H-C & Lee, C-Y 2015, A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. in F Dielacher, W Pribyl & G Hueber (eds), ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference., 7313837, European Solid-State Circuits Conference, vol. 2015-October, IEEE Computer Society, pp. 96-99, 41st European Solid-State Circuits Conference, ESSCIRC 2015, Graz, Austria, 14/09/15. https://doi.org/10.1109/ESSCIRC.2015.7313837

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. / Lee, Xin Ru; Yang, Chih Wen; Chen, Chih-Lung et al.
ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. ed. / Franz Dielacher; Wolfgang Pribyl; Gernot Hueber. IEEE Computer Society, 2015. p. 96-99 7313837 (European Solid-State Circuits Conference; Vol. 2015-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Chen-Yi

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AB - In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.

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Lee XR, Yang CW, Chen CL, Chang HC , Lee CY. A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. In Dielacher F, Pribyl W, Hueber G, editors, ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. IEEE Computer Society. 2015. p. 96-99. 7313837. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2015.7313837

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications

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