A 13 × W, 94 mK Resolution, CMOS PD ΔΣ M Temperature-to-Digital Converter With Power-Gating Technique

Ying Jie Huang*, Yu Chiao Huang, Yu Hao Chiu, Wen Pin Tsai, Yu Te Liao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a CMOS phase-domain delta-sigma modulator ( P D Δ Σ M) that digitizes temperaturedependent phase shifts resulting from driving a poly-phase filter (PPF) at a constant frequency. Closed-loop architecture with a power-gating technique is applied to improve linearity and power efficiency. The design is implemented in a 0.18 μ m CMOS process. The temperature sensor has an inaccuracy of ± 2.2°C(3σ) from -40°C to 85° C. Furthermore, the design achieves a resolution of 94 mK at 1 k S a/ s, while the chip area is 0.19 m m2. The power consumption is 13 μ W, resulting in an inaccuracy FoM of 161.1 n J%2.

Original languageEnglish
Title of host publicationESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
PublisherIEEE Computer Society
Pages17-20
Number of pages4
ISBN (Electronic)9798350304206
DOIs
StatePublished - 2023
Event49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal
Duration: 11 Sep 202314 Sep 2023

Publication series

NameEuropean Solid-State Circuits Conference
Volume2023-September
ISSN (Print)1930-8833

Conference

Conference49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
Country/TerritoryPortugal
CityLisbon
Period11/09/2314/09/23

Keywords

  • CMOS
  • delta-sigma modulator
  • phase domain
  • temperature sensor

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