TY - GEN
T1 - A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6% High Efficiency and Fast Transient Response
AU - Kuo, Yu Chen
AU - Wu, Hong Teng
AU - Chen, Guan Ye
AU - Chen, Ke Horng
AU - Zheng, Kuo Lin
AU - Li, Chih Chen
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper proposes an inverted pyramid trans-inductor voltage regulator (IP-TLVR) converter that can offer significant benefits, including extended duty cycle, reduced power loss, and lower voltage stress. Additionally, it exhibits superior transient performance without additional complex controls by using trans-inductor (TL). This architecture has two inductor current outputs, which greatly increase the power density. This topology features allow the inductor current to be auto-balanced. It is manufactured using a 0.18μ m BCD process, which achieves a peak efficiency of 93.6%, a maximum output current of 100A, and attains an 8μ s recovery time for a 90A/1μ s load transition.
AB - This paper proposes an inverted pyramid trans-inductor voltage regulator (IP-TLVR) converter that can offer significant benefits, including extended duty cycle, reduced power loss, and lower voltage stress. Additionally, it exhibits superior transient performance without additional complex controls by using trans-inductor (TL). This architecture has two inductor current outputs, which greatly increase the power density. This topology features allow the inductor current to be auto-balanced. It is manufactured using a 0.18μ m BCD process, which achieves a peak efficiency of 93.6%, a maximum output current of 100A, and attains an 8μ s recovery time for a 90A/1μ s load transition.
UR - http://www.scopus.com/inward/record.url?scp=85203603712&partnerID=8YFLogxK
U2 - 10.1109/VLSITechnologyandCir46783.2024.10631382
DO - 10.1109/VLSITechnologyandCir46783.2024.10631382
M3 - Conference contribution
AN - SCOPUS:85203603712
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Y2 - 16 June 2024 through 20 June 2024
ER -