A 12B 100MS/S low-power zero-crossing-based adc with current mismatch corrections

Tsung Heng Tsai*, Bo Yu Shiu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This work presents a 12b 100MS/s zero-crossing-based switched-capacitor CMOS pipelined analog-to-digital converter (ADC). The proposed ADC improves the resolution, power efficiency, and sample rate of the fully differential zero-crossing-based circuits and features a 90nm CMOS technology. Offset tolerance, current splitting, and a digital correction scheme were implemented to correct mismatches among current sources. Post-layout simulations show that the SNDR is 72.6dB when the input is close to the Nyquist rate. The power consumption is 20.8mW from a 1.2V supply and the figure-of-merit (FOM) is 59.6 fJ/conversion. The chip area occupies 2.88mm 2.

Original languageEnglish
Pages (from-to)77-83
Number of pages7
JournalInternational Journal of Electrical Engineering
Volume19
Issue number2
StatePublished - Apr 2012

Keywords

  • ADC
  • CBSC
  • Low power
  • Pipelined adc
  • Switched-capacitor
  • ZCBC

Fingerprint

Dive into the research topics of 'A 12B 100MS/S low-power zero-crossing-based adc with current mismatch corrections'. Together they form a unique fingerprint.

Cite this