A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks

Tsung Han Wu; Ching Liang Yeh; Yi Shan Huang; Shyh Jye Jou

doi:10.1109/ISCAS58744.2024.10558369

A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks

Tsung Han Wu
, Ching Liang Yeh
, Yi Shan Huang
, Shyh Jye Jou^*

^*Corresponding author for this work

National Yang Ming Chiao Tung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10^-8 at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.

Original language	English
Title of host publication	ISCAS 2024 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350330991
DOIs	https://doi.org/10.1109/ISCAS58744.2024.10558369
State	Published - 2024
Event	2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore Duration: 19 May 2024 → 22 May 2024

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Country/Territory	Singapore
City	Singapore
Period	19/05/24 → 22/05/24

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

6G
Terahertz
dynamic decoding
low-density parity check (LDPC) decoder
message-passing schedule

Access to Document

10.1109/ISCAS58744.2024.10558369

Cite this

Wu, T. H., Yeh, C. L., Huang, Y. S., & Jou, S. J. (2024). A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. In ISCAS 2024 - IEEE International Symposium on Circuits and Systems (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS58744.2024.10558369

Wu, Tsung Han ; Yeh, Ching Liang ; Huang, Yi Shan et al. / A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks",

abstract = "This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10-8 at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.",

keywords = "6G, Terahertz, dynamic decoding, low-density parity check (LDPC) decoder, message-passing schedule",

author = "Wu, \{Tsung Han\} and Yeh, \{Ching Liang\} and Huang, \{Yi Shan\} and Jou, \{Shyh Jye\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",

year = "2024",

doi = "10.1109/ISCAS58744.2024.10558369",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2024 - IEEE International Symposium on Circuits and Systems",

address = "美國",

}

Wu, TH, Yeh, CL, Huang, YS & Jou, SJ 2024, A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. in ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, Singapore, 19/05/24. https://doi.org/10.1109/ISCAS58744.2024.10558369

A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. / Wu, Tsung Han; Yeh, Ching Liang; Huang, Yi Shan et al.
ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks

AU - Wu, Tsung Han

AU - Yeh, Ching Liang

AU - Huang, Yi Shan

AU - Jou, Shyh Jye

PY - 2024

Y1 - 2024

N2 - This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10-8 at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.

AB - This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10-8 at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.

KW - 6G

KW - Terahertz

KW - dynamic decoding

KW - low-density parity check (LDPC) decoder

KW - message-passing schedule

UR - https://www.scopus.com/pages/publications/85198524929

U2 - 10.1109/ISCAS58744.2024.10558369

DO - 10.1109/ISCAS58744.2024.10558369

M3 - Conference contribution

AN - SCOPUS:85198524929

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2024 - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024

Y2 - 19 May 2024 through 22 May 2024

ER -

Wu TH, Yeh CL, Huang YS, Jou SJ. A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. In ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2024. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS58744.2024.10558369

A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks

Abstract

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UN SDGs

Keywords

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