@inproceedings{28c2069827cb41199cb84848dbb29713,
title = "A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks",
abstract = "This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10-8 at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.",
keywords = "6G, dynamic decoding, low-density parity check (LDPC) decoder, message-passing schedule, Terahertz",
author = "Wu, {Tsung Han} and Yeh, {Ching Liang} and Huang, {Yi Shan} and Jou, {Shyh Jye}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",
year = "2024",
doi = "10.1109/ISCAS58744.2024.10558369",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2024 - IEEE International Symposium on Circuits and Systems",
address = "United States",
}
