A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals

Yu Zhe Wang; Yao Pin Wang; Yi Chung Wu; Chia Hsiang Yang

doi:10.1109/VLSIC.2018.8502321

A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals

Yu Zhe Wang, Yao Pin Wang, Yi Chung Wu, Chia Hsiang Yang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This work presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively-sensed signals. The chip delivers a throughput of 573-to-2,901KS/s for reconstructing physiological signals. It dissipates 12.6mW at 87 MHz at 0.6V. Compared to the state-of-the-art designs, the chip achieves a 5.7-to-14x higher throughput with 5-to-11x lower energy for the target reconstruction SNR (RSNR) ≥ 15dB.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	261-262
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502321
State	Published - 22 Oct 2018
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Conference

Conference	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

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10.1109/VLSIC.2018.8502321

Cite this

Wang, Y. Z., Wang, Y. P., Wu, Y. C., & Yang, C. H. (2018). A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 261-262). Article 8502321 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502321

@inproceedings{4a613c1dd62f4882a9c9982e4f00d71e,

title = "A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals",

abstract = "This work presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively-sensed signals. The chip delivers a throughput of 573-to-2,901KS/s for reconstructing physiological signals. It dissipates 12.6mW at 87 MHz at 0.6V. Compared to the state-of-the-art designs, the chip achieves a 5.7-to-14x higher throughput with 5-to-11x lower energy for the target reconstruction SNR (RSNR) ≥ 15dB.",

author = "Wang, {Yu Zhe} and Wang, {Yao Pin} and Wu, {Yi Chung} and Yang, {Chia Hsiang}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

month = oct,

day = "22",

doi = "10.1109/VLSIC.2018.8502321",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "261--262",

booktitle = "2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018",

address = "United States",

}

Wang, YZ, Wang, YP, Wu, YC & Yang, CH 2018, A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502321, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 261-262, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIC.2018.8502321

A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. / Wang, Yu Zhe; Wang, Yao Pin; Wu, Yi Chung et al.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 261-262 8502321 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals

AU - Wang, Yu Zhe

AU - Wang, Yao Pin

AU - Wu, Yi Chung

AU - Yang, Chia Hsiang

PY - 2018/10/22

Y1 - 2018/10/22

N2 - This work presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively-sensed signals. The chip delivers a throughput of 573-to-2,901KS/s for reconstructing physiological signals. It dissipates 12.6mW at 87 MHz at 0.6V. Compared to the state-of-the-art designs, the chip achieves a 5.7-to-14x higher throughput with 5-to-11x lower energy for the target reconstruction SNR (RSNR) ≥ 15dB.

AB - This work presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively-sensed signals. The chip delivers a throughput of 573-to-2,901KS/s for reconstructing physiological signals. It dissipates 12.6mW at 87 MHz at 0.6V. Compared to the state-of-the-art designs, the chip achieves a 5.7-to-14x higher throughput with 5-to-11x lower energy for the target reconstruction SNR (RSNR) ≥ 15dB.

UR - http://www.scopus.com/inward/record.url?scp=85056886437&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2018.8502321

DO - 10.1109/VLSIC.2018.8502321

M3 - Conference contribution

AN - SCOPUS:85056886437

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 261

EP - 262

BT - 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018

Y2 - 18 June 2018 through 22 June 2018

ER -

Wang YZ, Wang YP, Wu YC, Yang CH. A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 261-262. 8502321. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2018.8502321

A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals

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