A 12.5 gbps CMOS input sampler for serial link receiver front end

Shyh-Jye Jou; Chih Hsien Lin; Yen I. Wang

doi:10.1109/ISCAS.2005.1464773

A 12.5 gbps CMOS input sampler for serial link receiver front end

Shyh-Jye Jou^*, Chih Hsien Lin, Yen I. Wang

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper presents a high-speed CMOS input sampler used for serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3x oversampliing is utilized for data recovery, there are 24 input samplers in receiver front end. These input samplers are implemented in TSMC0.18um 1P6M process with area of 252*162 um ² . The circuits can operate at maximum input data rate of 12.7 Gbps with differential signal of 300 mV using supply voltage of 1.8V.

Original language	English
Article number	1464773
Pages (from-to)	1055-1058
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464773
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "A 12.5 gbps CMOS input sampler for serial link receiver front end",

abstract = " This paper presents a high-speed CMOS input sampler used for serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3x oversampliing is utilized for data recovery, there are 24 input samplers in receiver front end. These input samplers are implemented in TSMC0.18um 1P6M process with area of 252*162 um 2 . The circuits can operate at maximum input data rate of 12.7 Gbps with differential signal of 300 mV using supply voltage of 1.8V.",

author = "Shyh-Jye Jou and Lin, {Chih Hsien} and Wang, {Yen I.}",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ISCAS.2005.1464773",

language = "English",

pages = "1055--1058",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

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T1 - A 12.5 gbps CMOS input sampler for serial link receiver front end

AU - Jou, Shyh-Jye

AU - Lin, Chih Hsien

AU - Wang, Yen I.

PY - 2005/12/1

Y1 - 2005/12/1

N2 - This paper presents a high-speed CMOS input sampler used for serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3x oversampliing is utilized for data recovery, there are 24 input samplers in receiver front end. These input samplers are implemented in TSMC0.18um 1P6M process with area of 252*162 um 2 . The circuits can operate at maximum input data rate of 12.7 Gbps with differential signal of 300 mV using supply voltage of 1.8V.

AB - This paper presents a high-speed CMOS input sampler used for serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3x oversampliing is utilized for data recovery, there are 24 input samplers in receiver front end. These input samplers are implemented in TSMC0.18um 1P6M process with area of 252*162 um 2 . The circuits can operate at maximum input data rate of 12.7 Gbps with differential signal of 300 mV using supply voltage of 1.8V.

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U2 - 10.1109/ISCAS.2005.1464773

DO - 10.1109/ISCAS.2005.1464773

M3 - Conference article

AN - SCOPUS:67649086476

SN - 0271-4310

SP - 1055

EP - 1058

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1464773

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A 12.5 gbps CMOS input sampler for serial link receiver front end

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