A 12-BIT PULSE-SHRINKING TIME-TO-DIGITAL CONVERTER WITH TIMING SKEW CALIBRATION

A 12-bit three-step cyclic time-to-digital converter (TDC) with high energy efficiency is presented in this work. To compensate for the resolution errors in different stages, a pulse-shrinking-locked loop (PSLL) calibration scheme is proposed, which can realize coarse stage and fine stage calibrations using a single set of circuits. Moreover, it does not require an external precise clock as a reference and increases the tolerance for timing skew. The proposed TDC achieves high resolution and wide dynamic range and is designed in TSMC CMOS 0.35μm technology with a conversion rate of 100 kS/s. The measurement results show a wide dynamic range of 102.4 ns. The integral non-linearity (INL) and differential non-linearity (DNL) are-0.34 to 0.29 LSB and-0.81 to 0.86 LSB, respectively. With a power consumption of 1.18 mW, the figure of merit (FoM) for each conversion step is 6.39 pJ/conversion step.