TY - GEN
T1 - A 11.5-Gbps LDPC decoder based on CP-PEG code construction
AU - Chen, Chih Lung
AU - Lin, Kao Shou
AU - Chang, Hsie-Chia
AU - Fang, Wai-Chi
AU - Lee, Chen-Yi
PY - 2009/12/1
Y1 - 2009/12/1
N2 - In this paper, a LDPC decoder chip based on CP-PEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high code-rate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 × 1.4 mm2. The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.
AB - In this paper, a LDPC decoder chip based on CP-PEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high code-rate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 × 1.4 mm2. The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.
KW - High throughput
KW - LDPC
KW - Sequential scheduling
UR - http://www.scopus.com/inward/record.url?scp=72849143369&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2009.5325933
DO - 10.1109/ESSCIRC.2009.5325933
M3 - Conference contribution
AN - SCOPUS:72849143369
SN - 9781424443536
T3 - ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
SP - 412
EP - 415
BT - ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
T2 - 35th European Solid-State Circuits Conference, ESSCIRC 2009
Y2 - 14 September 2009 through 18 September 2009
ER -