A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su; Wei-Zen Chen; Pei Si Wu; Yu Hsian Chen; Chao Cheng Lee; Shyh-Jye Jou

doi:10.1109/CICC.2013.6658469

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su, Wei-Zen Chen, Pei Si Wu, Yu Hsian Chen, Chao Cheng Lee, Shyh-Jye Jou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI_pp input data jitter, the recovered clock jitter at 2GHz is 2.94ps_rms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm².

Original language	English
Title of host publication	Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781467361460
DOIs	https://doi.org/10.1109/CICC.2013.6658469
State	Published - 7 Nov 2013
Event	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States Duration: 22 Sep 2013 → 25 Sep 2013

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
Country/Territory	United States
City	San Jose, CA
Period	22/09/13 → 25/09/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/CICC.2013.6658469

Cite this

Su, M. C., Chen, W.-Z., Wu, P. S., Chen, Y. H., Lee, C. C., & Jou, S.-J. (2013). A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 Article 6658469 (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658469

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title = "A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression",

abstract = "A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock jitter at 2GHz is 2.94psrms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm2.",

author = "Su, {Ming Chiuan} and Wei-Zen Chen and Wu, {Pei Si} and Chen, {Yu Hsian} and Lee, {Chao Cheng} and Shyh-Jye Jou",

year = "2013",

month = nov,

day = "7",

doi = "10.1109/CICC.2013.6658469",

language = "English",

isbn = "9781467361460",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",

address = "美國",

note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",

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Su, MC, Chen, W-Z, Wu, PS, Chen, YH, Lee, CC & Jou, S-J 2013, A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013., 6658469, Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, United States, 22/09/13. https://doi.org/10.1109/CICC.2013.6658469

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. / Su, Ming Chiuan; Chen, Wei-Zen; Wu, Pei Si et al.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. 6658469 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chen, Wei-Zen

AU - Wu, Pei Si

AU - Chen, Yu Hsian

AU - Lee, Chao Cheng

AU - Jou, Shyh-Jye

PY - 2013/11/7

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N2 - A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock jitter at 2GHz is 2.94psrms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm2.

AB - A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock jitter at 2GHz is 2.94psrms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm2.

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Su MC, Chen WZ, Wu PS, Chen YH, Lee CC, Jou SJ. A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc. 2013. 6658469. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC.2013.6658469

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

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