A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor

Kuo Jung Sun*, Zuo-Min Tsai , Kun You Lin, Huei Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

19 Scopus citations

Abstract

A noise-reduction design method using parallel-resonant technique is demonstrated to improve the noise performance of a 10-GHz CMOS cascode low-noise amplifier, which is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology. Measurements show a power gain of 10 dB with noise figure of 2.5 dB at 10.8 GHz, which is believed to be the lowest NF among the LNAs using bulk 0.18 μm CMOS at this frequency.

Original languageEnglish
Title of host publication2007 IEEE MTT-S International Microwave Symposium Digest
Pages1795-1798
Number of pages4
DOIs
StatePublished - 2 Oct 2007
Event2007 IEEE MTT-S International Microwave Symposium, IMS 2007 - Honolulu, HI, United States
Duration: 3 Jun 20078 Jun 2007

Publication series

NameIEEE MTT-S International Microwave Symposium Digest
ISSN (Print)0149-645X

Conference

Conference2007 IEEE MTT-S International Microwave Symposium, IMS 2007
Country/TerritoryUnited States
CityHonolulu, HI
Period3/06/078/06/07

Keywords

  • CMOS
  • Low-noise amplifier (LNA)

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