A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction

Keyphrases

• Noise Reduction 100%
• Aggressor 100%
• Spur 100%
• Active Noise Cancellation 100%
• Phase Noise Cancellation 100%
• Noise Floor 100%
• Dual Loop PLL 100%
• Low Phase Noise 50%
• Timing Control 50%
• Circuitry 50%
• Oscillator Basis 50%
• Delay Time 50%
• Ring Oscillator 50%
• Circuit Techniques 50%
• Reference Signal 50%
• Low Noise 50%
• Frequency Synthesizer 50%
• Injection Timing 50%
• Existing Techniques 50%
• Noise Cancellation 50%
• Reference Frequency 50%
• Wired Communication 50%
• Noise Level 50%
• Low-frequency Noise 50%
• Noise Suppression 50%
• Long Delay 50%
• Frequency Spurs 50%
• Wireless Communication Systems 50%
• Phase Detector 50%
• Delayed Matching 50%
• Noise Detection 50%
• Gain Matching 50%
• SoC Integration 50%
• Injection-locked PLL (ILPLL) 50%
• Reference Injection 50%
• High-frequency Stability 50%

Engineering

• Phase Locked Loop 100%
• Active Noise Cancellation 100%
• Phase Noise 60%
• Noise Cancellation 60%
• Noise Floor 40%
• Delay Time 20%
• Communication System 20%
• Wireless Communication 20%
• System-on-Chip 20%
• Reference Signal 20%
• Reference Frequency 20%
• Frequency Noise 20%
• Noise Suppression 20%
• Noise Level 20%
• Discriminator 20%
• Oscillator 20%
• Phase Detector 20%