A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su; Wei-Zen Chen; Pei Si Wu; Yu Hsiang Chen; Chao Cheng Lee; Shyh-Jye Jou

doi:10.1109/TCSI.2014.2367573

A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su, Wei-Zen Chen, Pei Si Wu, Yu Hsiang Chen, Chao Cheng Lee, Shyh-Jye Jou

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI_pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps_rms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm² only. It dissipates 12.4 mW from 1 V supply.

Original language	English
Article number	06977996
Pages (from-to)	743-751
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	62
Issue number	3
DOIs	https://doi.org/10.1109/TCSI.2014.2367573
State	Published - 1 Mar 2015

Keywords

Burst-mode clock and data recovery (BMCDR)
Gated-VCO (GVCO)
Gigabit passive optical network (GPON)
Phase-locked loop (PLL)

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10.1109/TCSI.2014.2367573

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title = "A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression",

abstract = "A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UIpp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 psrms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm2 only. It dissipates 12.4 mW from 1 V supply.",

keywords = "Burst-mode clock and data recovery (BMCDR), Gated-VCO (GVCO), Gigabit passive optical network (GPON), Phase-locked loop (PLL)",

author = "Su, {Ming Chiuan} and Wei-Zen Chen and Wu, {Pei Si} and Chen, {Yu Hsiang} and Lee, {Chao Cheng} and Shyh-Jye Jou",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.",

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doi = "10.1109/TCSI.2014.2367573",

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T1 - A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression

AU - Su, Ming Chiuan

AU - Chen, Wei-Zen

AU - Wu, Pei Si

AU - Chen, Yu Hsiang

AU - Lee, Chao Cheng

AU - Jou, Shyh-Jye

PY - 2015/3/1

Y1 - 2015/3/1

N2 - A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UIpp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 psrms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm2 only. It dissipates 12.4 mW from 1 V supply.

AB - A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UIpp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 psrms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm2 only. It dissipates 12.4 mW from 1 V supply.

KW - Burst-mode clock and data recovery (BMCDR)

KW - Gated-VCO (GVCO)

KW - Gigabit passive optical network (GPON)

KW - Phase-locked loop (PLL)

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DO - 10.1109/TCSI.2014.2367573

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ER -

A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression

Abstract

Keywords

UN SDGs

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