A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps rms . The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm 2 only. It dissipates 12.4 mW from 1 V supply.
|Number of pages||9|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 Mar 2015|
- Burst-mode clock and data recovery (BMCDR)
- Gated-VCO (GVCO)
- Gigabit passive optical network (GPON)
- Phase-locked loop (PLL)