A 10-bit asynchronous SAR ADC with scalable conversion time in 0.18μm CMOS

Po Chiang Tung, Duen Ting Fan, Tsung Heng Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, a 10b 100-to-500 kS/s asynchronous SAR ADC is proposed and prototyped in 0.18 μm CMOS. The supply voltage is scaled down appropriately for different sampling speeds to minimize the power consumption. At a 0.5-V supply voltage and a 100 kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424 nW, resultin g in a figure of merit of 7.9 fJ/conversion-step. The ADC core occupies an active area of only 0.077 mm2.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1454-1457
Number of pages4
ISBN (Electronic)9781479953400
DOIs
StatePublished - 29 Jul 2016
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 22 May 201625 May 2016

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2016-July
ISSN (Print)0271-4310

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/TerritoryCanada
CityMontreal
Period22/05/1625/05/16

Keywords

  • Asynchronous
  • Low power
  • Low voltage
  • Metastability
  • SAR ADC

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