@inproceedings{d1764d7db6224dd4b8c99bcca3341c89,
title = "A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter",
abstract = "This paper presents a 10-bit all binary-weighted current-steering digital-to-analog converter (DAC) with low-glitch and low-power properties. Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS process, and dissipates 19mW from a single 1.8V power supply.",
keywords = "Binary-weighted, Current Mode, DAC, Low glitch",
author = "Chou, {Fang Ting} and Chen, {Zong Yi} and Chung-Chih Hung",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 27th IEEE International System on Chip Conference, SOCC 2014 ; Conference date: 02-09-2014 Through 05-09-2014",
year = "2014",
month = nov,
day = "5",
doi = "10.1109/SOCC.2014.6948933",
language = "English",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "231--235",
editor = "Kaijian Shi and Thomas Buchner and Danella Zhao and Ramalingam Sridhar",
booktitle = "International System on Chip Conference",
address = "美國",
}