A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network

Chih-Lung Chen; Sheng Jhan Wu; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ASSCC.2014.7008902

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network

Chih-Lung Chen^*, Sheng Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1∼100Mb/s with power consumption of 0.5∼9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.

Original language	English
Title of host publication	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	229-232
Number of pages	4
ISBN (Electronic)	9781479940905
DOIs	https://doi.org/10.1109/ASSCC.2014.7008902
State	Published - 10 Nov 2014
Event	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan Duration: 10 Nov 2014 → 12 Nov 2014

Publication series

Name	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/Territory	Taiwan
City	Kaohsiung
Period	10/11/14 → 12/11/14

Access to Document

10.1109/ASSCC.2014.7008902

Cite this

Chen, C.-L., Wu, S. J., Chang, H.-C., & Lee, C.-Y. (2014). A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers (pp. 229-232). Article 7008902 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2014.7008902

Chen, Chih-Lung ; Wu, Sheng Jhan ; Chang, Hsie-Chia et al. / A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 229-232 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

@inproceedings{2f3267fe827444898a8d3a1889e0befa,

title = "A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network",

abstract = "A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1∼100Mb/s with power consumption of 0.5∼9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.",

author = "Chih-Lung Chen and Wu, {Sheng Jhan} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2014",

month = nov,

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doi = "10.1109/ASSCC.2014.7008902",

language = "English",

series = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",

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note = "2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 ; Conference date: 10-11-2014 Through 12-11-2014",

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Chen, C-L, Wu, SJ, Chang, H-C & Lee, C-Y 2014, A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. in 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers., 7008902, 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 229-232, 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, Kaohsiung, Taiwan, 10/11/14. https://doi.org/10.1109/ASSCC.2014.7008902

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. / Chen, Chih-Lung; Wu, Sheng Jhan; Chang, Hsie-Chia et al.
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. p. 229-232 7008902 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Chen CL, Wu SJ, Chang HC , Lee CY. A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. p. 229-232. 7008902. (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). doi: 10.1109/ASSCC.2014.7008902

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network

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