For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This chapter presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-μW power while generating output clock of 401.8–431.31-MHz and exhibiting a phase noise of −105.7 dBc/Hz at 1-MHz frequency offset with 20 μs locking time.