TY - GEN
T1 - A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications
AU - Hong, Hao-Chiao
AU - Chiu, Yi
PY - 2018/4/26
Y1 - 2018/4/26
N2 - This paper presents a 10-bit SAR ADC operating at a supply voltage (vDD) of 0.225 V and down to 0.2 V for self-sustainable IoT applications. We propose an ultra-low VDD temperature-compensated bias current generator for biasing the comparator against temperature variation to address the temperature-dependent issue of the MOSFETs operating in the subthreshold region. In addition, the design fixes the positive input terminal of the comparator at VDD to bias the input transistor pair of the comparator with a sufficient voltage headroom at such a low VDD. The double-boosted with leakage reduction sampling switch is also proposed to address the severe leakage issue at low sampling rates. A test chip has been fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm2. Measurement results show that at 0.225V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR with the Nyquist input frequency is 49.8 dB at 450 S/s and 0.225V. The whole ADC totally consumes 0.85 nW at 0.225 V including the circuit leakages. It corresponds to an FoM of 8.0 fJ/conv.-step.
AB - This paper presents a 10-bit SAR ADC operating at a supply voltage (vDD) of 0.225 V and down to 0.2 V for self-sustainable IoT applications. We propose an ultra-low VDD temperature-compensated bias current generator for biasing the comparator against temperature variation to address the temperature-dependent issue of the MOSFETs operating in the subthreshold region. In addition, the design fixes the positive input terminal of the comparator at VDD to bias the input transistor pair of the comparator with a sufficient voltage headroom at such a low VDD. The double-boosted with leakage reduction sampling switch is also proposed to address the severe leakage issue at low sampling rates. A test chip has been fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm2. Measurement results show that at 0.225V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR with the Nyquist input frequency is 49.8 dB at 450 S/s and 0.225V. The whole ADC totally consumes 0.85 nW at 0.225 V including the circuit leakages. It corresponds to an FoM of 8.0 fJ/conv.-step.
UR - http://www.scopus.com/inward/record.url?scp=85057135016&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2018.8351329
DO - 10.1109/ISCAS.2018.8351329
M3 - Conference contribution
AN - SCOPUS:85057135016
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Y2 - 27 May 2018 through 30 May 2018
ER -