A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

K. K. Young, S. Y. Wu, C. C. Wu, C. H. Wang, C. T. Lin, J. Y. Cheng, M. Chiang, S. H. Chen, T. C. Lo, Y. S. Chen, J. H. Chen, L. J. Chen, S. Y. Hou, J. J. Liaw, T. E. Chang, C. S. Hou, J. Shih, S. M. Jeng, H. C. Hsieh, Y. KuT. Yen, H. Tao, L. C. Chao, S. Shue, S. M. Jang, T. C. Ong, C. H. Yu, M. S. Liang, C. H. Diaz, J. Y.C. Sun

Research output: Contribution to journalConference articlepeer-review

62 Scopus citations


A leading-edge 0.13 μm CMOS technology using 193nm lithography and Cu/low-k interconnect is described in this paper. High performance 80nm core devices use 17 Å nitrided oxide for 1.0-1.2V operation. These devices deliver unloaded 8.5ps gate delay @1.2V. This technology also supports general ASIC applications with 20 Å oxide for 1.2-1.5V operation and low-standby power applications with 26 Å for 1.5V operation, respectively. Dual gate oxides of 50 or 65 Å are also supported for 2.5V or 3.3V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high-density 1P3M 2.43 μm2 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.

Original languageEnglish
Pages (from-to)563-566
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 2000
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 10 Dec 200013 Dec 2000


Dive into the research topics of 'A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications'. Together they form a unique fingerprint.

Cite this