A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement

Wei-Zen Chen, Po I. Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

A sub-ps ΔΣ TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and ΔΣ TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm2.

Original languageEnglish
Title of host publicationESSCIRC 2016
Subtitle of host publication42nd European Solid-State Circuits Conference
PublisherIEEE Computer Society
Pages347-350
Number of pages4
ISBN (Electronic)9781509029723
DOIs
StatePublished - 18 Oct 2016
Event42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Switzerland
Duration: 12 Sep 201615 Sep 2016

Publication series

NameEuropean Solid-State Circuits Conference
Volume2016-October
ISSN (Print)1930-8833

Conference

Conference42nd European Solid-State Circuits Conference, ESSCIRC 2016
Country/TerritorySwitzerland
CityLausanne
Period12/09/1615/09/16

Keywords

  • BIST
  • PLL
  • Phase Noise Measurement
  • sub-ps ΔΣ TDC

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