8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Yi Wei Chiu; Jihi Yu Lin; Ming Hsien Tu; Shyh-Jye Jou; Ching Te Chuang

doi:10.1109/ISLPED.2011.5993631

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Yi Wei Chiu^*, Jihi Yu Lin, Ming Hsien Tu, Shyh-Jye Jou, Ching Te Chuang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

21 Scopus citations

Abstract

This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.

Original language	English
Title of host publication	IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages	169-174
Number of pages	6
DOIs	https://doi.org/10.1109/ISLPED.2011.5993631
State	Published - 19 Sep 2011
Event	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan Duration: 1 Aug 2011 → 3 Aug 2011

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Conference

Conference	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Country/Territory	Japan
City	Fukuoka
Period	1/08/11 → 3/08/11

Keywords

Data-Aware Write Operation
SRAM
Static Random Access Memory

Access to Document

10.1109/ISLPED.2011.5993631

Cite this

Chiu, Y. W., Lin, J. Y., Tu, M. H., Jou, S.-J., & Chuang, C. T. (2011). 8T Single-ended sub-threshold SRAM with cross-point data-aware write operation. In IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 (pp. 169-174). Article 5993631 (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1109/ISLPED.2011.5993631

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title = "8T Single-ended sub-threshold SRAM with cross-point data-aware write operation",

abstract = "This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.",

keywords = "Data-Aware Write Operation, SRAM, Static Random Access Memory",

author = "Chiu, {Yi Wei} and Lin, {Jihi Yu} and Tu, {Ming Hsien} and Shyh-Jye Jou and Chuang, {Ching Te}",

year = "2011",

month = sep,

day = "19",

doi = "10.1109/ISLPED.2011.5993631",

language = "English",

isbn = "9781612846590",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "169--174",

booktitle = "IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011",

note = "17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 ; Conference date: 01-08-2011 Through 03-08-2011",

}

Chiu, YW, Lin, JY, Tu, MH, Jou, S-J & Chuang, CT 2011, 8T Single-ended sub-threshold SRAM with cross-point data-aware write operation. in IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011., 5993631, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 169-174, 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011, Fukuoka, Japan, 1/08/11. https://doi.org/10.1109/ISLPED.2011.5993631

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation. / Chiu, Yi Wei; Lin, Jihi Yu; Tu, Ming Hsien et al.
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. p. 169-174 5993631 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chuang, Ching Te

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N2 - This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.

AB - This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.

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ER -

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

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Keywords

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