80nm SOI CMOS parameter extraction for BSIMPD

K. Goto; Pin Su; Y. Tagawa; T. Sugii; Chen-Ming Hu

doi:10.1109/SOIC.2001.957982

80nm SOI CMOS parameter extraction for BSIMPD

K. Goto^*, Pin Su, Y. Tagawa, T. Sugii, Chen-Ming Hu

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.

Original language	English
Pages	55-56
Number of pages	2
DOIs	https://doi.org/10.1109/SOIC.2001.957982
State	Published - Aug 2002
Event	2001 IEEE International SOI Conference - Durango, CO, United States Duration: 1 Oct 2001 → 4 Oct 2001

Conference

Conference	2001 IEEE International SOI Conference
Country/Territory	United States
City	Durango, CO
Period	1/10/01 → 4/10/01

Access to Document

10.1109/SOIC.2001.957982

Cite this

@conference{776a28fd1c97436c8cec331a040d553b,

title = "80nm SOI CMOS parameter extraction for BSIMPD",

abstract = "A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.",

author = "K. Goto and Pin Su and Y. Tagawa and T. Sugii and Chen-Ming Hu",

year = "2002",

month = aug,

doi = "10.1109/SOIC.2001.957982",

language = "English",

pages = "55--56",

note = "2001 IEEE International SOI Conference ; Conference date: 01-10-2001 Through 04-10-2001",

}

TY - CONF

T1 - 80nm SOI CMOS parameter extraction for BSIMPD

AU - Goto, K.

AU - Su, Pin

AU - Tagawa, Y.

AU - Sugii, T.

AU - Hu, Chen-Ming

PY - 2002/8

Y1 - 2002/8

N2 - A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.

AB - A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.

UR - http://www.scopus.com/inward/record.url?scp=0035158802&partnerID=8YFLogxK

U2 - 10.1109/SOIC.2001.957982

DO - 10.1109/SOIC.2001.957982

M3 - Paper

AN - SCOPUS:0035158802

SP - 55

EP - 56

T2 - 2001 IEEE International SOI Conference

Y2 - 1 October 2001 through 4 October 2001

ER -

80nm SOI CMOS parameter extraction for BSIMPD

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this