3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi

Bo Jheng Shih; Yu Ming Pan; Hao Tung Chung; Chieh Ling Lee; I. Chun Hsieh; Nein Chih Lin; Chih Chao Yang; Po Tsang Huang; Hung Ming Chen; Chiao Yen Wang; Huan Yu Chiu; Huang Chung Cheng; Chang Hong Shen; Wen Fa Wu; Tuo Hung Hou; Kuan Neng Chen; Chenming Hu

doi:10.1109/VLSITechnologyandCir46783.2024.10631506

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm²) Single-Crystalline Si on SiO₂ by Elevated-Epi

Bo Jheng Shih, Yu Ming Pan, Hao Tung Chung, Chieh Ling Lee, I. Chun Hsieh, Nein Chih Lin, Chih Chao Yang^*, Po Tsang Huang^*, Hung Ming Chen, Chiao Yen Wang, Huan Yu Chiu, Huang Chung Cheng, Chang Hong Shen, Wen Fa Wu, Tuo Hung Hou, Kuan Neng Chen^*, Chenming Hu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size (25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.

Original language	English
Title of host publication	2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350361469
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631506
State	Published - 2024
Event	2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States Duration: 16 Jun 2024 → 20 Jun 2024

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Country/Territory	United States
City	Honolulu
Period	16/06/24 → 20/06/24

Keywords

3DIC
Elevated Epi
Laser recrystallization

Access to Document

10.1109/VLSITechnologyandCir46783.2024.10631506

Cite this

Shih, B. J., Pan, Y. M., Chung, H. T., Lee, C. L., Hsieh, I. C., Lin, N. C., Yang, C. C., Huang, P. T., Chen, H. M., Wang, C. Y., Chiu, H. Y., Cheng, H. C., Shen, C. H., Wu, W. F., Hou, T. H., Chen, K. N., & Hu, C. (2024). 3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm²) Single-Crystalline Si on SiO₂ by Elevated-Epi. In 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631506

Shih, Bo Jheng ; Pan, Yu Ming ; Chung, Hao Tung et al. / 3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm²) Single-Crystalline Si on SiO₂ by Elevated-Epi. 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{bac70bb031c64431936159f2df6641bf,

title = "3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi",

abstract = "The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size (25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.",

keywords = "3DIC, Elevated Epi, Laser recrystallization",

author = "Shih, \{Bo Jheng\} and Pan, \{Yu Ming\} and Chung, \{Hao Tung\} and Lee, \{Chieh Ling\} and Hsieh, \{I. Chun\} and Lin, \{Nein Chih\} and Yang, \{Chih Chao\} and Huang, \{Po Tsang\} and Chen, \{Hung Ming\} and Wang, \{Chiao Yen\} and Chiu, \{Huan Yu\} and Cheng, \{Huang Chung\} and Shen, \{Chang Hong\} and Wu, \{Wen Fa\} and Hou, \{Tuo Hung\} and Chen, \{Kuan Neng\} and Chenming Hu",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 ; Conference date: 16-06-2024 Through 20-06-2024",

year = "2024",

doi = "10.1109/VLSITechnologyandCir46783.2024.10631506",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024",

address = "美國",

}

Shih, BJ, Pan, YM, Chung, HT, Lee, CL, Hsieh, IC, Lin, NC, Yang, CC, Huang, PT , Chen, HM, Wang, CY, Chiu, HY, Cheng, HC, Shen, CH, Wu, WF, Hou, TH, Chen, KN & Hu, C 2024, 3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm²) Single-Crystalline Si on SiO₂ by Elevated-Epi. in 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024, Honolulu, United States, 16/06/24. https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631506

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm²) Single-Crystalline Si on SiO₂ by Elevated-Epi. / Shih, Bo Jheng; Pan, Yu Ming; Chung, Hao Tung et al.
2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi

AU - Shih, Bo Jheng

AU - Pan, Yu Ming

AU - Chung, Hao Tung

AU - Lee, Chieh Ling

AU - Hsieh, I. Chun

AU - Lin, Nein Chih

AU - Yang, Chih Chao

AU - Huang, Po Tsang

AU - Chen, Hung Ming

AU - Wang, Chiao Yen

AU - Chiu, Huan Yu

AU - Cheng, Huang Chung

AU - Shen, Chang Hong

AU - Wu, Wen Fa

AU - Hou, Tuo Hung

AU - Chen, Kuan Neng

AU - Hu, Chenming

PY - 2024

Y1 - 2024

N2 - The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size (25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.

AB - The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size (25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.

KW - 3DIC

KW - Elevated Epi

KW - Laser recrystallization

UR - https://www.scopus.com/pages/publications/85203593394

U2 - 10.1109/VLSITechnologyandCir46783.2024.10631506

DO - 10.1109/VLSITechnologyandCir46783.2024.10631506

M3 - Conference contribution

AN - SCOPUS:85203593394

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024

Y2 - 16 June 2024 through 20 June 2024

ER -

Shih BJ, Pan YM, Chung HT, Lee CL, Hsieh IC, Lin NC et al. 3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm²) Single-Crystalline Si on SiO₂ by Elevated-Epi. In 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc. 2024. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46783.2024.10631506