3D finite-element analysis of metal nanocrystal memories variations

Jonathan T. Shaw, Tuo-Hung Hou, Hassan Raza, Edwin C. Kan

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    We have shown the process variation effects from nanocrystal size, density, registry and gate length in 20 - 90 nm metal nanocrystal memory technology by 3D finite-element analysis. Conventional 1D analysis in the gate stack will result in severe miscalculation of bit-error-rate due to neglecting the fringing fields and percolation path in the memory cell. We also present the statistical metrology on memory windows from nanocrystal placement control and the use of nanowire devices. We conclude that the self-assembled nanocrystals in the gate stack can fit the parametric yield required for 20nm technology.

    Original languageEnglish
    Title of host publicationProceedings - 2009 13th International Workshop on Computational Electronics, IWCE 2009
    DOIs
    StatePublished - 2009
    Event2009 13th International Workshop on Computational Electronics, IWCE 2009 - Beijing, China
    Duration: 27 May 200929 May 2009

    Publication series

    NameProceedings - 2009 13th International Workshop on Computational Electronics, IWCE 2009

    Conference

    Conference2009 13th International Workshop on Computational Electronics, IWCE 2009
    Country/TerritoryChina
    CityBeijing
    Period27/05/0929/05/09

    Keywords

    • Bit-error rate
    • Flash memory
    • Metal nanocrystals
    • Process variation

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