3D 65nm CMOS with 320°C microwave dopant activation

Yao Jen Lee; Yu Lun Lu; Fu Kuo Hsueh; Kuo Chin Huang; Chia Chen Wan; Tz Yen Cheng; Ming Hung Han; Jeff M. Kowalski; Jeff E. Kowalski; Dawei Heh; Hsi Ta Chuang; Yi-Ming Li; Tien-Sheng Chao; Ching Yi Wu; Fu Liang Yang

doi:10.1109/IEDM.2009.5424426

3D 65nm CMOS with 320°C microwave dopant activation

Yao Jen Lee^*, Yu Lun Lu, Fu Kuo Hsueh, Kuo Chin Huang, Chia Chen Wan, Tz Yen Cheng, Ming Hung Han, Jeff M. Kowalski, Jeff E. Kowalski, Dawei Heh, Hsi Ta Chuang, Yi-Ming Li, Tien-Sheng Chao, Ching Yi Wu, Fu Liang Yang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF₂ for p-MOS TFTs and P³¹ for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

Original language	English
Title of host publication	2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
Pages	2.3.1-2.3.4
DOIs	https://doi.org/10.1109/IEDM.2009.5424426
State	Published - 2009
Event	2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States Duration: 7 Dec 2009 → 9 Dec 2009

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2009 International Electron Devices Meeting, IEDM 2009
Country/Territory	United States
City	Baltimore, MD
Period	7/12/09 → 9/12/09

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10.1109/IEDM.2009.5424426

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Lee, Y. J., Lu, Y. L., Hsueh, F. K., Huang, K. C., Wan, C. C., Cheng, T. Y., Han, M. H., Kowalski, J. M., Kowalski, J. E., Heh, D., Chuang, H. T., Li, Y.-M., Chao, T.-S., Wu, C. Y., & Yang, F. L. (2009). 3D 65nm CMOS with 320°C microwave dopant activation. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest (pp. 2.3.1-2.3.4). Article 54244263 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2009.5424426

@inproceedings{f6346085e37d4bf7935dfa11742eea49,

title = "3D 65nm CMOS with 320°C microwave dopant activation",

abstract = "For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.",

author = "Lee, {Yao Jen} and Lu, {Yu Lun} and Hsueh, {Fu Kuo} and Huang, {Kuo Chin} and Wan, {Chia Chen} and Cheng, {Tz Yen} and Han, {Ming Hung} and Kowalski, {Jeff M.} and Kowalski, {Jeff E.} and Dawei Heh and Chuang, {Hsi Ta} and Yi-Ming Li and Tien-Sheng Chao and Wu, {Ching Yi} and Yang, {Fu Liang}",

year = "2009",

doi = "10.1109/IEDM.2009.5424426",

language = "English",

isbn = "9781424456406",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "2.3.1--2.3.4",

booktitle = "2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest",

note = "2009 International Electron Devices Meeting, IEDM 2009 ; Conference date: 07-12-2009 Through 09-12-2009",

}

Lee, YJ, Lu, YL, Hsueh, FK, Huang, KC, Wan, CC, Cheng, TY, Han, MH, Kowalski, JM, Kowalski, JE, Heh, D, Chuang, HT, Li, Y-M , Chao, T-S, Wu, CY & Yang, FL 2009, 3D 65nm CMOS with 320°C microwave dopant activation. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 54244263, Technical Digest - International Electron Devices Meeting, IEDM, pp. 2.3.1-2.3.4, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 7/12/09. https://doi.org/10.1109/IEDM.2009.5424426

3D 65nm CMOS with 320°C microwave dopant activation. / Lee, Yao Jen; Lu, Yu Lun; Hsueh, Fu Kuo et al.
2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. p. 2.3.1-2.3.4 54244263 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 3D 65nm CMOS with 320°C microwave dopant activation

AU - Lee, Yao Jen

AU - Lu, Yu Lun

AU - Hsueh, Fu Kuo

AU - Huang, Kuo Chin

AU - Wan, Chia Chen

AU - Cheng, Tz Yen

AU - Han, Ming Hung

AU - Kowalski, Jeff M.

AU - Kowalski, Jeff E.

AU - Heh, Dawei

AU - Chuang, Hsi Ta

AU - Li, Yi-Ming

AU - Chao, Tien-Sheng

AU - Wu, Ching Yi

AU - Yang, Fu Liang

PY - 2009

Y1 - 2009

N2 - For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

AB - For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

UR - http://www.scopus.com/inward/record.url?scp=77952418685&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2009.5424426

DO - 10.1109/IEDM.2009.5424426

M3 - Conference contribution

AN - SCOPUS:77952418685

SN - 9781424456406

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 2.3.1-2.3.4

BT - 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest

T2 - 2009 International Electron Devices Meeting, IEDM 2009

Y2 - 7 December 2009 through 9 December 2009

ER -

3D 65nm CMOS with 320°C microwave dopant activation

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