3.5ns CMOS 64K ECL RAM at 77°K

S. E. Schuster; T. I. Chappell; B. A. Chappell; J. W. Allan; J. Y.C. Sun; S. P. Klepner; R. L. Franch; P. F. Greier; P. J. Restle

3.5ns CMOS 64K ECL RAM at 77°K

S. E. Schuster^*, T. I. Chappell, B. A. Chappell, J. W. Allan, J. Y.C. Sun, S. P. Klepner, R. L. Franch, P. F. Greier, P. J. Restle

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

4 Scopus citations

Abstract

A 3.5-ns 64K CMOS RAM operated at 77 K has been described. The chip was fabricated in a dual 0.5-μm gate polysilicon process optimized for low-temperature operation. The design features asynchronous receivers capable of interfacing low-voltage ECL signal levels. Liquid-nitrogen operation of the RAM offers higher-speed operation than previously reported at the 64K level of integration for any technology.

Original language	English
Pages	17-18
Number of pages	2
State	Published - 1988
Event	1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan Duration: 22 Aug 1988 → 24 Aug 1988

Conference

Conference	1988 Symposium on VLSI Circuits - Digest of Technical Papers
City	Tokyo, Japan
Period	22/08/88 → 24/08/88

Cite this

@conference{f905d35fa5214d5c86e4e44fe3d1d8e5,

title = "3.5ns CMOS 64K ECL RAM at 77°K",

abstract = "A 3.5-ns 64K CMOS RAM operated at 77 K has been described. The chip was fabricated in a dual 0.5-μm gate polysilicon process optimized for low-temperature operation. The design features asynchronous receivers capable of interfacing low-voltage ECL signal levels. Liquid-nitrogen operation of the RAM offers higher-speed operation than previously reported at the 64K level of integration for any technology.",

author = "Schuster, {S. E.} and Chappell, {T. I.} and Chappell, {B. A.} and Allan, {J. W.} and Sun, {J. Y.C.} and Klepner, {S. P.} and Franch, {R. L.} and Greier, {P. F.} and Restle, {P. J.}",

year = "1988",

language = "English",

pages = "17--18",

note = "null ; Conference date: 22-08-1988 Through 24-08-1988",

}

TY - CONF

T1 - 3.5ns CMOS 64K ECL RAM at 77°K

AU - Schuster, S. E.

AU - Chappell, T. I.

AU - Chappell, B. A.

AU - Allan, J. W.

AU - Sun, J. Y.C.

AU - Klepner, S. P.

AU - Franch, R. L.

AU - Greier, P. F.

AU - Restle, P. J.

PY - 1988

Y1 - 1988

N2 - A 3.5-ns 64K CMOS RAM operated at 77 K has been described. The chip was fabricated in a dual 0.5-μm gate polysilicon process optimized for low-temperature operation. The design features asynchronous receivers capable of interfacing low-voltage ECL signal levels. Liquid-nitrogen operation of the RAM offers higher-speed operation than previously reported at the 64K level of integration for any technology.

AB - A 3.5-ns 64K CMOS RAM operated at 77 K has been described. The chip was fabricated in a dual 0.5-μm gate polysilicon process optimized for low-temperature operation. The design features asynchronous receivers capable of interfacing low-voltage ECL signal levels. Liquid-nitrogen operation of the RAM offers higher-speed operation than previously reported at the 64K level of integration for any technology.

UR - http://www.scopus.com/inward/record.url?scp=0024168448&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0024168448

SP - 17

EP - 18

Y2 - 22 August 1988 through 24 August 1988

ER -

3.5ns CMOS 64K ECL RAM at 77°K

Abstract

Conference

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