32 × 64 SPAD Imager Using 2-bit In-Pixel Stack-Based Memory for Low-Light Imaging

Hsi Hao Huang*, Tzu Yun Huang, Chun Hsien Liu, Sheng Di Lin, Chen Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


This article presents a high-detection rate single-photon avalanche diode (SPAD) imaging chip designed for photon-sensing applications. The test chip includes two essential design techniques: passive quenching active clock-drive reset (PQACR) to maximize the detection window and in- pixel stack-based memory (IPSM) to reduce the effective dead time. PQACR architecture achieves 97.5% coverage detection window with minimal photon loss using a single transistor, while the IPSM architecture reduces the effective dead time from 33 to 22 ns with 28 transistors, overcoming the dead-time limitation issue in photon-counting designs. A test chip with a 32 × 64 array has been fabricated in Taiwan semiconductor manufacturing company (TSMC) 0.18- μm HV CMOS process. Experimental results demonstrate that the proposed chip achieves less dead time and photon loss, making it well suited for high-speed and low-light imaging applications.

Original languageEnglish
Pages (from-to)19272-19281
Number of pages10
JournalIEEE Sensors Journal
Issue number17
StatePublished - 1 Sep 2023


  • In-pixel stack-based memory (IPSM)
  • low-light imaging
  • passive quenching active clock-drive reset (PQACR)
  • photon counting
  • single-photon avalanche diode (SPAD)


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