28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms

Wei Shen Hsu; Po-Tsang Huang; Shang Lin Wu; Ching Te Chuang; Wei Hwang; Ming Hsien Tu; Ming Yu Yin

doi:10.1109/VLSI-DAT.2016.7482551

28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms

Wei Shen Hsu, Po-Tsang Huang, Shang Lin Wu, Ching Te Chuang, Wei Hwang, Ming Hsien Tu, Ming Yu Yin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, an ultra-low-power near-/sub-threshold first-in-first-out (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512×16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482551
State	Published - 31 May 2016
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/16 → 27/04/16

Access to Document

10.1109/VLSI-DAT.2016.7482551

Cite this

Hsu, W. S., Huang, P.-T., Wu, S. L., Chuang, C. T., Hwang, W., Tu, M. H., & Yin, M. Y. (2016). 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 Article 7482551 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482551

Hsu, Wei Shen ; Huang, Po-Tsang ; Wu, Shang Lin et al. / 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

@inproceedings{4fa0f79ebafc435780c046c2d36a256d,

title = "28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms",

abstract = "In this paper, an ultra-low-power near-/sub-threshold first-in-first-out (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512×16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.",

author = "Hsu, {Wei Shen} and Po-Tsang Huang and Wu, {Shang Lin} and Chuang, {Ching Te} and Wei Hwang and Tu, {Ming Hsien} and Yin, {Ming Yu}",

year = "2016",

month = may,

day = "31",

doi = "10.1109/VLSI-DAT.2016.7482551",

language = "English",

series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

address = "United States",

note = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

}

Hsu, WS, Huang, P-T, Wu, SL, Chuang, CT, Hwang, W, Tu, MH & Yin, MY 2016, 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482551, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 25/04/16. https://doi.org/10.1109/VLSI-DAT.2016.7482551

28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms. / Hsu, Wei Shen; Huang, Po-Tsang; Wu, Shang Lin et al.
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482551 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms

AU - Hsu, Wei Shen

AU - Huang, Po-Tsang

AU - Wu, Shang Lin

AU - Chuang, Ching Te

AU - Hwang, Wei

AU - Tu, Ming Hsien

AU - Yin, Ming Yu

PY - 2016/5/31

Y1 - 2016/5/31

N2 - In this paper, an ultra-low-power near-/sub-threshold first-in-first-out (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512×16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.

AB - In this paper, an ultra-low-power near-/sub-threshold first-in-first-out (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512×16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.

UR - http://www.scopus.com/inward/record.url?scp=84978414589&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2016.7482551

DO - 10.1109/VLSI-DAT.2016.7482551

M3 - Conference contribution

AN - SCOPUS:84978414589

T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Y2 - 25 April 2016 through 27 April 2016

ER -

Hsu WS, Huang PT, Wu SL, Chuang CT, Hwang W, Tu MH et al. 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482551. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482551

28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this