20.1 A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC Power Switch

Si Yi Li, Wei Chien Hung, Tz Wun Wang, Ya Ting Hsu, Ke Horng Chen, Kuo Lin Zheng, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Silicon carbide (SiC) MOSFET devices offer better performance in high-voltage (HV) and high-current applications, such as electric vehicles, railways, and motor drives due to their low losses, low impedance, high blocking voltage, and good high temperature tolerance. Recently, the rated 1700V SiC is used in a power conversion system (PCS) for efficient energy storage. Compared to 800V and 1200V SiCs, high voltage and fast switching SiC MOSFET will cause large dv/dt (> 100kV/μs) and di/dt (>10textkA/mus) High dv/dt at the switch node will couple the common mode transient (CMT) disturbances to the high side transmitter (TX) through an isolation barrier parasitic capacitance CPAR. Meanwhile, a large di/dt on the parasitic inductance LPAR will cause abnormal ringing and couple to the TX through CPAR (upper left of Fig. 20.1.1). Although the isolated gate drivers (IGD) with the transformer galvanic isolation have good common-mode transient immunity (CMTI) [1], their duty cycle is limited to 50% due the regeneration of the drive voltage being controlled by the duty cycle [2]. In contrast, capacitive isolation is not limited by the duty cycle, but instead, requires the modulator at the TX circuit to transmit the drive signal. When CMT disturbance occurs, a common mode current (ICM), proportional to dv/dt at the switching node, flows through CPAR to the TX circuit and affects the conventional demodulation circuit of the receiver (RX) circuit (top in Fig. 20.1.1). The dv/dt ranges from over 100textkV/muS for 1700V SiC to 40kV/μs for 800V SiC. In the case of large R1(2), the induced ICM will cause large common-mode shift (textCMS=ICM starR1(2)). A large CMS can cause the VIP or VIN of the comparator in the demodulator to exceed the input common mode range (ICMR) and the demodulator cannot receive the correct control signal for some CMT periods. Due to the absence of correct control signals, fault tolerance mechanisms can limit the runtime within a hysteresis window [3]. However, under high voltage, the noise coupling to the gate of the low-side SiC MOSFET, through the gate-to-drain capacitance CGD, will become larger due to the higher dv/dt, which will increase the possibility of abnormal turn-on. State-of-the-art gate drivers require an external negative supply voltage, VEE to turn off the SiC MOSFET to suppress abnormal turn-on. In addition, conventional discrete VEE voltage sources are set more negative to overcome discrete parasitic resistance effects. However, efficiency is reduced if VEE is too low.

Original languageEnglish
Title of host publication2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages302-304
Number of pages3
ISBN (Electronic)9781665428002
DOIs
StatePublished - 2023
Event2023 IEEE International Solid-State Circuits Conference, ISSCC 2023 - Virtual, Online, United States
Duration: 19 Feb 202323 Feb 2023

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2023-February
ISSN (Print)0193-6530

Conference

Conference2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
Country/TerritoryUnited States
CityVirtual, Online
Period19/02/2323/02/23

Fingerprint

Dive into the research topics of '20.1 A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC Power Switch'. Together they form a unique fingerprint.

Cite this