CMOS single-photon avalanche diode (SPAD) array is a high-timing-resolution photon-counting image sensor. Pixel size shrinkage for high image resolution is highly desirable but hindered by the lowered photon-detection-probability (PDP) as the edge area becomes significant. We propose and demonstrate a parameter-free method for simulating PDP with the edge effect. Considering the doping profile, electric field, photon generation, and trigger probability distributions in two dimensions, the PDP reduction at the device edge is analyzed in a quantitative way. Besides, a novel guard-ring design for enhancing PDP of small SPAD has been proposed and simulated by our method. A threefold enhancement was obtained with the newly designed guard-ring structure compared with the original one. Our work is useful for developing small-pitch SPAD array for high-resolution imaging applications.
- Charge carrier processes
- Image edge detection
- Mathematical models
- photo detector
- photon-detection probability (PDP)
- Semiconductor device modeling
- single-photon avalanche diode (SPAD)
- Single-photon avalanche diodes
- small pitch SPAD array.