1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation

Masud Rana Sk; Sunanda Thunder; Franz Müller; Nellie Laleni; Yannick Raffel; Maximilian Lederer; Luca Pirro; Talha Chohan; Jing Hua Hsuen; Tian Li Wu; Konrad Seidel; Thomas Kämpfe; Sourav De; Bhaswar Chakrabarti

doi:10.1109/TNANO.2023.3295093

1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation

Masud Rana Sk, Sunanda Thunder, Franz Müller, Nellie Laleni, Yannick Raffel, Maximilian Lederer, Luca Pirro, Talha Chohan, Jing Hua Hsuen, Tian Li Wu^*, Konrad Seidel, Thomas Kämpfe, Sourav De^*, Bhaswar Chakrabarti^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (IBL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

Original language	English
Pages (from-to)	424-429
Number of pages	6
Journal	IEEE Transactions on Nanotechnology
Volume	22
DOIs	https://doi.org/10.1109/TNANO.2023.3295093
State	Published - 2023

Keywords

1F-1T
FeFET
HfO
memory array
vector-matrix-multiplication

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10.1109/TNANO.2023.3295093

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Sk, M. R., Thunder, S., Müller, F., Laleni, N., Raffel, Y., Lederer, M., Pirro, L., Chohan, T., Hsuen, J. H., Wu, T. L., Seidel, K., Kämpfe, T., De, S., & Chakrabarti, B. (2023). 1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation. IEEE Transactions on Nanotechnology, 22, 424-429. https://doi.org/10.1109/TNANO.2023.3295093

@article{207625abfcdc4fcbb5adb0d0665f2960,

title = "1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation",

abstract = "This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (IBL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.",

keywords = "1F-1T, FeFET, HfO, memory array, vector-matrix-multiplication",

author = "Sk, {Masud Rana} and Sunanda Thunder and Franz M{\"u}ller and Nellie Laleni and Yannick Raffel and Maximilian Lederer and Luca Pirro and Talha Chohan and Hsuen, {Jing Hua} and Wu, {Tian Li} and Konrad Seidel and Thomas K{\"a}mpfe and Sourav De and Bhaswar Chakrabarti",

note = "Publisher Copyright: {\textcopyright} 2002-2012 IEEE.",

year = "2023",

doi = "10.1109/TNANO.2023.3295093",

language = "English",

volume = "22",

pages = "424--429",

journal = "IEEE Transactions on Nanotechnology",

issn = "1536-125X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

Sk, MR, Thunder, S, Müller, F, Laleni, N, Raffel, Y, Lederer, M, Pirro, L, Chohan, T, Hsuen, JH, Wu, TL, Seidel, K, Kämpfe, T, De, S & Chakrabarti, B 2023, '1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation', IEEE Transactions on Nanotechnology, vol. 22, pp. 424-429. https://doi.org/10.1109/TNANO.2023.3295093

TY - JOUR

T1 - 1F-1T Array

T2 - Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation

AU - Sk, Masud Rana

AU - Thunder, Sunanda

AU - Müller, Franz

AU - Laleni, Nellie

AU - Raffel, Yannick

AU - Lederer, Maximilian

AU - Pirro, Luca

AU - Chohan, Talha

AU - Hsuen, Jing Hua

AU - Wu, Tian Li

AU - Seidel, Konrad

AU - Kämpfe, Thomas

AU - De, Sourav

AU - Chakrabarti, Bhaswar

PY - 2023

Y1 - 2023

N2 - This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (IBL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

AB - This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (IBL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

KW - 1F-1T

KW - FeFET

KW - HfO

KW - memory array

KW - vector-matrix-multiplication

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U2 - 10.1109/TNANO.2023.3295093

DO - 10.1109/TNANO.2023.3295093

M3 - Article

AN - SCOPUS:85164803418

SN - 1536-125X

VL - 22

SP - 424

EP - 429

JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

ER -

1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation

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Keywords

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