1.2μm Bi-CMOS technology with high performance ECL

H. Iwai*, Y. Niitsu, G. Sasaki, M. Norishima, K. Shino, Y. Unno, K. Tsugaru, H. Hara, Y. Sugimoto, K. Kanzaki

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

1.2μm Bi-CMOS technology with ECL gate for high speed device has been developed. A process is carefully optimized for obtaining the best performance of ECL gate without degrading 1.2μm Bi-CMOS performance and mass productivity.

Original languageEnglish
Title of host publicationESSDERC 1987 - 17th European Solid State Device Research Conference
PublisherIEEE Computer Society
Pages29-32
Number of pages4
ISBN (Electronic)0444704779
ISBN (Print)9780444704771
StatePublished - 1987
Event17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy
Duration: 14 Sep 198717 Sep 1987

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference17th European Solid State Device Research Conference, ESSDERC 1987
Country/TerritoryItaly
CityBologna
Period14/09/8717/09/87

Fingerprint

Dive into the research topics of '1.2μm Bi-CMOS technology with high performance ECL'. Together they form a unique fingerprint.

Cite this