TY - GEN
T1 - 10Gbps decision feedback equalizer with dynamic lookahead decision loop
AU - Lin, Yu Chun
AU - Shiue, Muh Tian
AU - Jou, Shyh-Jye
PY - 2009/10/26
Y1 - 2009/10/26
N2 - Decision feedback equalizer (DFE) uses a feedback path to cancel post-cursor ISI, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10Gbps multiplexer-based lookahead DFE.
AB - Decision feedback equalizer (DFE) uses a feedback path to cancel post-cursor ISI, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10Gbps multiplexer-based lookahead DFE.
UR - http://www.scopus.com/inward/record.url?scp=70350179485&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2009.5118136
DO - 10.1109/ISCAS.2009.5118136
M3 - Conference contribution
AN - SCOPUS:70350179485
SN - 9781424438280
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1839
EP - 1842
BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Y2 - 24 May 2009 through 27 May 2009
ER -