100MHz pipelined CMOS comparator for flash A/D conversion.

Jieh-Tsorng Wu; Bruce A. Wooley

doi:10.1109/CICC.1988.20892

100MHz pipelined CMOS comparator for flash A/D conversion.

Jieh-Tsorng Wu^*, Bruce A. Wooley

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

A description is given of the design of a VLSI-compatible CMOS comparator wherein voltage comparisons are accomplished directly by means of regenerative sensing. Input sampling, offset correction and common-mode cancellation have been incorporated into a pipelined cascade of regenerative sense amplifiers. Integrated in a standard 2-μm CMOS technology, the comparator operates at a maximum sampling rate of over 100 MHz, while dissipating only 3.6 mW of power from a single +5-V supply.

Original language	English
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1988.20892
State	Published - 1 Dec 1988

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10.1109/CICC.1988.20892

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title = "100MHz pipelined CMOS comparator for flash A/D conversion.",

abstract = "A description is given of the design of a VLSI-compatible CMOS comparator wherein voltage comparisons are accomplished directly by means of regenerative sensing. Input sampling, offset correction and common-mode cancellation have been incorporated into a pipelined cascade of regenerative sense amplifiers. Integrated in a standard 2-μm CMOS technology, the comparator operates at a maximum sampling rate of over 100 MHz, while dissipating only 3.6 mW of power from a single +5-V supply.",

author = "Jieh-Tsorng Wu and Wooley, {Bruce A.}",

year = "1988",

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doi = "10.1109/CICC.1988.20892",

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AU - Wu, Jieh-Tsorng

AU - Wooley, Bruce A.

PY - 1988/12/1

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N2 - A description is given of the design of a VLSI-compatible CMOS comparator wherein voltage comparisons are accomplished directly by means of regenerative sensing. Input sampling, offset correction and common-mode cancellation have been incorporated into a pipelined cascade of regenerative sense amplifiers. Integrated in a standard 2-μm CMOS technology, the comparator operates at a maximum sampling rate of over 100 MHz, while dissipating only 3.6 mW of power from a single +5-V supply.

AB - A description is given of the design of a VLSI-compatible CMOS comparator wherein voltage comparisons are accomplished directly by means of regenerative sensing. Input sampling, offset correction and common-mode cancellation have been incorporated into a pipelined cascade of regenerative sense amplifiers. Integrated in a standard 2-μm CMOS technology, the comparator operates at a maximum sampling rate of over 100 MHz, while dissipating only 3.6 mW of power from a single +5-V supply.

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U2 - 10.1109/CICC.1988.20892

DO - 10.1109/CICC.1988.20892

M3 - Conference article

AN - SCOPUS:0024139131

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

SN - 0886-5930

ER -

100MHz pipelined CMOS comparator for flash A/D conversion.

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