10-bit SAR ADC with novel pseudo-random capacitor switching scheme

Pai Hsiang Hsu; Yueh Ru Lee; Chung Chih Hung

doi:10.1109/VLSI-DAT.2019.8741534

10-bit SAR ADC with novel pseudo-random capacitor switching scheme

Pai Hsiang Hsu, Yueh Ru Lee, Chung Chih Hung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a pseudo-random capacitor switching scheme. Taking 1% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-μm 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68μW. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93μW. With a sampling rate of 1MS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102μW. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.

Original language	English
Title of host publication	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728106557
DOIs	https://doi.org/10.1109/VLSI-DAT.2019.8741534
State	Published - Apr 2019
Event	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan Duration: 22 Apr 2019 → 25 Apr 2019

Publication series

Name	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/19 → 25/04/19

Keywords

High-performance
Low power
Pseudo-random
Successive-approximation-register analog-to-digital converter

Access to Document

10.1109/VLSI-DAT.2019.8741534

Cite this

Hsu, P. H., Lee, Y. R., & Hung, C. C. (2019). 10-bit SAR ADC with novel pseudo-random capacitor switching scheme. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 Article 8741534 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741534

@inproceedings{cfbeda806c914371b2272e48dc1d0b05,

title = "10-bit SAR ADC with novel pseudo-random capacitor switching scheme",

abstract = "This paper presents a pseudo-random capacitor switching scheme. Taking 1% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-μm 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68μW. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93μW. With a sampling rate of 1MS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102μW. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.",

keywords = "High-performance, Low power, Pseudo-random, Successive-approximation-register analog-to-digital converter",

author = "Hsu, {Pai Hsiang} and Lee, {Yueh Ru} and Hung, {Chung Chih}",

year = "2019",

month = apr,

doi = "10.1109/VLSI-DAT.2019.8741534",

language = "English",

series = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

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note = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 ; Conference date: 22-04-2019 Through 25-04-2019",

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Hsu, PH, Lee, YR & Hung, CC 2019, 10-bit SAR ADC with novel pseudo-random capacitor switching scheme. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741534, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 22/04/19. https://doi.org/10.1109/VLSI-DAT.2019.8741534

10-bit SAR ADC with novel pseudo-random capacitor switching scheme. / Hsu, Pai Hsiang; Lee, Yueh Ru; Hung, Chung Chih.
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741534 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Yueh Ru

AU - Hung, Chung Chih

PY - 2019/4

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N2 - This paper presents a pseudo-random capacitor switching scheme. Taking 1% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-μm 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68μW. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93μW. With a sampling rate of 1MS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102μW. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.

AB - This paper presents a pseudo-random capacitor switching scheme. Taking 1% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-μm 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68μW. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93μW. With a sampling rate of 1MS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102μW. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.

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M3 - Conference contribution

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T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Y2 - 22 April 2019 through 25 April 2019

ER -

10-bit SAR ADC with novel pseudo-random capacitor switching scheme

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Keywords

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