1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology

Tien Y. Lo; Chung-Chih Hung

doi:10.1109/ISCAS.2007.378787

1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology

Tien Y. Lo^*, Chung-Chih Hung

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mV_pp differential input Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.

Original language	American English
Article number	4253507
Pages (from-to)	3792-3795
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2007.378787
State	Published - 27 May 2007
Event	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 27 May 2007 → 30 May 2007

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title = "1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology",

abstract = "This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.",

author = "Lo, {Tien Y.} and Chung-Chih Hung",

year = "2007",

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doi = "10.1109/ISCAS.2007.378787",

language = "American English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

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T1 - 1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology

AU - Lo, Tien Y.

AU - Hung, Chung-Chih

PY - 2007/5/27

Y1 - 2007/5/27

N2 - This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.

AB - This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.

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DO - 10.1109/ISCAS.2007.378787

M3 - Conference article

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 4253507

T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology

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