0.5 V DD digitally controlled oscillators design with compensation techniques for PVT variations

Chia Wen Chang; Shyh-Jye Jou; Yuan Hua Chu

doi:10.1109/ASICON.2011.6157278

0.5 V _DD digitally controlled oscillators design with compensation techniques for PVT variations

Chia Wen Chang^*, Shyh-Jye Jou, Yuan Hua Chu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a low voltage and low power digitally controlled oscillator (DCO) with not only wide frequency range and high frequency resolution but also compensation techniques against PVT variations. The frequency range of the 0.5 V _DD DCO, implemented in GP-65 nm LVT CMOS process, is from 278 MHz to 25 MHz for portable applications and consumes only 148 μW at 278 MHz and 28.5 μW at 25 MHz. Even in a dirty V _DD /GND condition, the peak-to-peak and RMS period jitter are 98.7 and 12.7 ps, respectively. In addition, with compensation techniques used in this work, the effective frequency range is increased by 1.786 times. As a result, compensation techniques in this work are very suitable for the demand of robust design, especially in low-voltage systems or wide PVT environments.

Original language	English
Title of host publication	Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Pages	606-609
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2011.6157278
State	Published - 1 Dec 2011
Event	2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China Duration: 25 Oct 2011 → 28 Oct 2011

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	2011 IEEE 9th International Conference on ASIC, ASICON 2011
Country/Territory	China
City	Xiamen
Period	25/10/11 → 28/10/11

Keywords

All-digital phase-locked loop
compensation techniques
digitally controlled oscillators
low voltage
PVT variations

Access to Document

10.1109/ASICON.2011.6157278

Cite this

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title = "0.5 V DD digitally controlled oscillators design with compensation techniques for PVT variations",

abstract = " This paper presents a low voltage and low power digitally controlled oscillator (DCO) with not only wide frequency range and high frequency resolution but also compensation techniques against PVT variations. The frequency range of the 0.5 V DD DCO, implemented in GP-65 nm LVT CMOS process, is from 278 MHz to 25 MHz for portable applications and consumes only 148 μW at 278 MHz and 28.5 μW at 25 MHz. Even in a dirty V DD /GND condition, the peak-to-peak and RMS period jitter are 98.7 and 12.7 ps, respectively. In addition, with compensation techniques used in this work, the effective frequency range is increased by 1.786 times. As a result, compensation techniques in this work are very suitable for the demand of robust design, especially in low-voltage systems or wide PVT environments.",

keywords = "All-digital phase-locked loop, compensation techniques, digitally controlled oscillators, low voltage, PVT variations",

author = "Chang, {Chia Wen} and Shyh-Jye Jou and Chu, {Yuan Hua}",

year = "2011",

month = dec,

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doi = "10.1109/ASICON.2011.6157278",

language = "English",

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series = "Proceedings of International Conference on ASIC",

pages = "606--609",

booktitle = "Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011",

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Chang, CW, Jou, S-J & Chu, YH 2011, 0.5 V _DD digitally controlled oscillators design with compensation techniques for PVT variations. in Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011., 6157278, Proceedings of International Conference on ASIC, pp. 606-609, 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, 25/10/11. https://doi.org/10.1109/ASICON.2011.6157278

0.5 V _DD digitally controlled oscillators design with compensation techniques for PVT variations. / Chang, Chia Wen; Jou, Shyh-Jye; Chu, Yuan Hua.
Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. 2011. p. 606-609 6157278 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a low voltage and low power digitally controlled oscillator (DCO) with not only wide frequency range and high frequency resolution but also compensation techniques against PVT variations. The frequency range of the 0.5 V DD DCO, implemented in GP-65 nm LVT CMOS process, is from 278 MHz to 25 MHz for portable applications and consumes only 148 μW at 278 MHz and 28.5 μW at 25 MHz. Even in a dirty V DD /GND condition, the peak-to-peak and RMS period jitter are 98.7 and 12.7 ps, respectively. In addition, with compensation techniques used in this work, the effective frequency range is increased by 1.786 times. As a result, compensation techniques in this work are very suitable for the demand of robust design, especially in low-voltage systems or wide PVT environments.

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