We introduce a 0.12 μm nMOS technology with multi-Vth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 μm nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1998|
|Event||Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 6 Dec 1998 → 9 Dec 1998