0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications

Bing-Yue Tsui*, Chia Pin Lin, Chih Feng Huang, Yi Hsuan Xiao

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    12 Scopus citations

    Abstract

    Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 μm channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.

    Original languageEnglish
    Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
    Pages911-914
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2005
    EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
    Duration: 5 Dec 20057 Dec 2005

    Publication series

    NameTechnical Digest - International Electron Devices Meeting, IEDM
    Volume2005
    ISSN (Print)0163-1918

    Conference

    ConferenceIEEE International Electron Devices Meeting, 2005 IEDM
    Country/TerritoryUnited States
    CityWashington, DC, MD
    Period5/12/057/12/05

    Fingerprint

    Dive into the research topics of '0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications'. Together they form a unique fingerprint.

    Cite this