0. 5- mu M-CHANNEL CMOS TECHNOLOGY OPTIMIZED FOR LIQUID-NITROGEN-TEMPERATURE OPERATION.

J. Y.C. Sun*, Y. Taur, R. H. Dennard, S. P. Klepner, L. K. Wang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations

Abstract

A high-performance 0. 5- mu m-channel CMOS technology optimized for liquid-nitrogen-temperature operation is described. It features dual polysilicon work functions (n** plus -poly for n-channel and p** plus -poly for p-channel transistors), 12. 5-nm gate oxide, deep threshold-adjust ion implantation for the n-channel device, shallow arsenic and boron source/drain diffusions, and thin self-aligned titanium silicide. The power supply voltage is chosen to be 2. 5 V based on performance, hot-carrier effects, and power dissipation considerations. The dual-work-function polysilicon gates are doped by the source/drain ion implantations. The sheet resistance of self-aligned silicide improves from rougly 4 OMEGA /sq at 300K to about 1 OMEGA /sq at 77K. Excellent device characteristics and functional ring oscillator circuits were obtained at 77K with roughly a 2 multiplied by improvement in both the speed and the power-delay product over the room-temperature technology operated at 300K.

Original languageEnglish
Pages (from-to)236-239
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1986

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