Terng-Yin Hsu (Inventor)
Research output: Patent
}
TY - PAT
T1 - 低延遲時間之餘切硬體結構及其計算方法
AU - Hsu, Terng-Yin
PY - 2013/12/1
Y1 - 2013/12/1
M3 - Patent
M1 - I417785
ER -