Projects per year
Personal profile
Research Interests
Mixed-signal Integrated Circuits, High Frequency Circuits, Communication System
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
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Collaborations and top research areas from the last five years
Projects
- 34 Finished
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Clock Generation and Timing Recovery for Advanced Data Link Transceivers
Chen, W.-Z. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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產學合作計畫-使用PAM-6 調變之高密度資料連結系統
Chen, W.-Z. (PI)
1/11/22 → 31/10/23
Project: Government Ministry › Other Government Ministry Institute
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Clock Generation and Timing Recovery for Advanced Data Link Transceivers
Chen, W.-Z. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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高能效仿生運算系統(2/2)
Chen, W.-Z. (PI)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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產學合作計畫-寬頻多模式有線傳輸發射機(2/2)
Chen, W.-Z. (PI)
1/11/21 → 31/10/22
Project: Government Ministry › Other Government Ministry Institute
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A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator with In-Situ Regulation for Energy-Efficient Spiking Neural Networks
Kao, S. H., Hung, Y. C., Wang, I. W., Liu, B. H., Chen, Y. C., Chang, T. S., Jou, S. J., Liu, C. N., Chen, H. M. & Chen, W. Z., 1 Aug 2026, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 73, 8, p. 5280-5290 11 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations -
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects
Mo, H. K., Huang, Y. P., Tu, Y. C. & Chen, W. Z., 2026, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 73, 3, p. 1913-1923 11 p.Research output: Contribution to journal › Article › peer-review
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A Single-Channel 12-GS/s 40.5-dB SNDR Time-Domain Stochastic Flash ADC
Wang, D. H., Wu, J. T. & Chen, W. Z., 1 Jul 2026, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 73, 7, p. 4545-4557 13 p.Research output: Contribution to journal › Article › peer-review
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Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis
Lin, S. S., Chen, S. Y., Huang, Y. P., Lin, T. C., Chen, H. M. & Chen, W. Z., 2025, 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings -Design, Automation and Test in Europe, DATE).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Dynamic ADC and Equalizer Adaptation with Background SNR Monitoring for a DSP-Based PAM-4 Receiver
Tu, Y. C., Kuo, R. Y. & Chen, W. Z., 2025, ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review