Projects per year
Personal profile
Research Interests
Mixed-signal Integrated Circuits, High Frequency Circuits, Communication System
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
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Dive into the research topics where Wei-Zen Chen is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
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Projects
- 34 Finished
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Clock Generation and Timing Recovery for Advanced Data Link Transceivers
Chen, W.-Z. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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產學合作計畫-使用PAM-6 調變之高密度資料連結系統
Chen, W.-Z. (PI)
1/11/22 → 31/10/23
Project: Government Ministry › Other Government Ministry Institute
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Clock Generation and Timing Recovery for Advanced Data Link Transceivers
Chen, W.-Z. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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高能效仿生運算系統(2/2)
Chen, W.-Z. (PI)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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產學合作計畫-寬頻多模式有線傳輸發射機(2/2)
Chen, W.-Z. (PI)
1/11/21 → 31/10/22
Project: Government Ministry › Other Government Ministry Institute
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Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC)
Chen, W. Z., Calhoun, B. H., Yang, C. H., Sen, S. & Yang, J., 2025, In: IEEE Journal of Solid-State Circuits. 60, 1, p. 5-8 4 p.Research output: Contribution to journal › Editorial
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A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction
Huang, Y. P., Lu, Y. S. & Chen, W. Z., 2024, In: IEEE Open Journal of Circuits and Systems. 5, p. 291-301 11 p.Research output: Contribution to journal › Article › peer-review
Open Access -
An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications
Effendrik, P. & Chen, W. Z., Mar 2024, In: Analog Integrated Circuits and Signal Processing. 118, 3, p. 523-537 15 p.Research output: Contribution to journal › Article › peer-review
Open Access -
A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement
Liu, Y. C., Chen, W. Z., Lee, Y. S., Chen, Y. H., Ming, S. & Lin, Y. H., 1 Oct 2023, In: IEEE Journal of Solid-State Circuits. 58, 10, p. 2801-2811 11 p.Research output: Contribution to journal › Article › peer-review
3 Scopus citations -
A 1.68-23.2-Gb/s Reference-Less Half-Rate Receiver With an ISI-Tolerant Unlimited Range Frequency Detector
Huang, Y. P., Chang, Y. W. & Chen, W. Z., 2022, In: IEEE Solid-State Circuits Letters. 5, p. 186-189 4 p.Research output: Contribution to journal › Article › peer-review
1 Scopus citations