Projects per year
Personal profile
Research Interests
Nanoscale Nonvolatile Memory, Molecular Electronics, Nanotechnology, Semiconductor Physics
Experience
Education/Academic qualification
PhD, Electrical Engineering, Cornell University
External positions
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Exploring the third dimension of Moore's Law: Cost-effective multilayer stackable 2D nanosheet transistor
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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Ultralow-energy computing-in-memory technology– A cross-layer optimization from key device development to neuromorphic chip design
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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A世代前瞻半導體技術專案計畫推動辦公室(2/2)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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Exploring the third dimension of Moore's Law: Cost-effective multilayer stackable 2D nanosheet transistor
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Ultralow-energy computing-in-memory technology– A cross-layer optimization from key device development to neuromorphic chip design
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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2D Materials-Based Static Random-Access Memory
Liu, C. J., Wan, Y., Li, L. J., Lin, C. P., Hou, T. H., Huang, Z. Y. & Hu, V. P. H., 2022, (Accepted/In press) In: Advanced Materials.Research output: Contribution to journal › Article › peer-review
5 Scopus citations -
A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer
Hong, M. C., Chang, Y. J., Hsin, Y. C., Liu, L. M., Chen, K. M., Su, Y. H., Chen, G. L., Yang, S. Y., Wang, I. J., Rahaman, S. Z., Lee, H. H., Chiu, S. C., Shih, C. Y., Wang, C. Y., Chen, F. M., Wei, J. H., Sheu, S. S., Lo, W. C., Lin, M. T., Wu, C. I., & 1 others, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., p. 379-380 2 p. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2022-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications
Liu, C., Li, S. T., Pan, T. L., Ni, C. E., Sung, Y., Hu, C. L., Chang, K. Y., Hou, T. H., Chang, T. S. & Jou, S. J., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
Area Scalable Hafnium-Zirconium-Oxide Ferroelectric Capacitor Using Low-Temperature Back-End-of-Line Compatible 40°C Annealing
Huang, T. S., Yeh, P. C., Yang, H. Y., Lin, Y. D., Tzeng, P. J., Sheu, S. S., Lo, W. C., Wu, C. I. & Hou, T. H., 2022, 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Bi2O2Se-Based True Random Number Generator for Security Applications
Liu, B., Chang, Y. F., Li, J., Liu, X., Wang, L. A., Verma, D., Liang, H., Zhu, H., Zhao, Y., Li, L. J., Hou, T. H. & Lai, C. S., 26 Apr 2022, In: ACS Nano. 16, 4, p. 6847-6857 11 p.Research output: Contribution to journal › Article › peer-review
4 Scopus citations
Prizes
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Ta-You Wu Memorial Award, National Science Council
Hou, Tuo-Hung (Recipient), 2013
Prize: Honorary award
Activities
- 1 Editorial work
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Scientific Reports (Event)
Tuo-Hung Hou (Member of editorial board)
1 Jan 2018 → 31 Dec 2018Activity: Publication peer-review and editorial work › Editorial work