Personal profile
Research Interests
· Computer Architecture
· Computer Systems
· Memory and Storage Systems
· Domain-specific Accelerators (GPU, Neural Processing Units)
Education/Academic qualification
PhD, Electrical Engineering, Purdue University
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Collaborations and top research areas from the last five years
Projects
- 6 Finished
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Transformer 類神經網路之軟硬體整合加速方案-子計畫二；高效能，低功耗邊緣AI計算加速器架構系統設計
Yeh, T.-T. (PI)
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫二；高效能，低功耗邊緣AI計算加速器架構系統設計
Yeh, T.-T. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫二；高效能，低功耗邊緣AI計算加速器架構系統設計
Yeh, T.-T. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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教育部智慧晶片系統與應用人才培育計畫-111年度智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-智慧終端裝置晶片系統與應用模組-邊緣 AI 加速器架構於微型深度學習網路模型
Yeh, T.-T. (PI)
1/04/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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Optimizing Domain-Specific Accelerator Hardware Resource Utilization
Yeh, T.-T. (PI)
1/11/21 → 1/01/23
Project: Government Ministry › Other Government Ministry Institute
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Leveraging Open-Channel SSDs for Enhanced Deep Learning Recommendation Model Performance
Shih, Y. C., Huang, Z. M., Ti, S. H., Yeh, T. T., Chen, S. H., Liang, Y. P. & Chen, T. Y., 2026, (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review
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AQB8: Energy-Efficient Ray Tracing Accelerator through Multi-Level Quantization
Huang, Y. C., Yang, C. P. & Yeh, T. T., 21 Jun 2025, ISCA 2025 - Proceedings of the 52nd Annual International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., p. 374-387 14 p. (Proceedings - International Symposium on Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access -
EDA: Energy-Efficient Inter-Layer Model Compilation for Edge DNN Inference Acceleration
Pao, B. R., Chen, I. C., Chang, E. H. & Yeh, T. T., 2025, Proceedings - 2025 IEEE International Symposium on High Performance Computer Architecture, HPCA 2025. IEEE Computer Society, p. 563-576 14 p. (Proceedings - International Symposium on High-Performance Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
StreamNet++: Memory-Efficient Streaming TinyML Model Compilation on Microcontrollers
Hsu, C. F., Zheng, H. S., Liu, Y. Y. & Yeh, T. T., 6 Jan 2025, In: ACM Transactions on Embedded Computing Systems. 24, 2, 23.Research output: Contribution to journal › Article › peer-review
Open Access2 Scopus citations -
OC-DLRM: Minimizing the I/O Traffic of DLRM Between Main Memory and OCSSD
Ti, S. H., Chen, T. Y., Yeh, T. T., Chen, S. H. & Liang, Y. P., 2024, 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings -Design, Automation and Test in Europe, DATE).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
2 Scopus citations